1. Field of the Invention
The present invention relates to display devices, and more particularly to a method for fabricating a transparent conducting electrode by employing a back exposure and a negative tone photoresist to reduce the number of full lithography steps and provide symmetric self alignment of a pixel electrode to a pixel in a thin film transistor array.
2. Description of the Related Art
In active matrix liquid crystal displays (AMLCDs), there is a strong economic incentive to reduce the number of photo processing steps and to improve the performance of thin film transistor (TFT) arrays. One way of improving the performance is to employ an insulating transparent planarizing polymer film (which may be photoimageable) to separate pixel electrodes from a substrate which includes TFT""s and associated wiring (see, e.g., U.S. Pat. No. 5,612,799, entitled: ACTIVE MATRIX TYPE ELECTRO-OPTICAL DEVICE, U.S. Pat. No. 5,780,871, entitled: TFT STRUCTURE INCLUDING A PHOTO-IMAGEABLE INSULATING LAYER FOR USE WITH LCDS AND IMAGE SENSORS, and U.S. Pat. No. 5,585,951 ACTIVE MATRIX SUBSTRATE). The approach described in these patents has the advantage of permitting the pixel electrode to overlap addressing lines since the planarizing material acts as an electrical insulator and reduces the capacitive coupling (if it is sufficiently thick). This, in turn, permits a higher aperture ratio, which is useful, but it does not significantly reduce the TFT array processing cost since there is no reduction in the number of photo processing steps needed. The number of photo processing steps typically needed is 5 with a planarizing polymer (see e.g., Sakamoto et al. pp.681-684 SID ""96 Digest, Zhong et al. pp. 971-974 SID ""98 Digest, and Nakabu et al., pp. 732-735 SID ""99 Digest). In all such processes, the final two steps pattern the planarizing polymer and the transparent conducting electrode material.
It is necessary in TFT array processing that the pixel electrode be well aligned to the data (also called signal) lines so that capacitive coupling between the pixel electrode and the data line are equal (symmetric) on each side. This permits the use of an appropriate drive inversion scheme, such as a dot inversion, to ensure that the image quality is not degraded by xe2x80x9ccross-talkxe2x80x9d(i.e., un-canceled capacitive coupling) between the data lines and the pixel electrode.
Therefore, a need exists for a method for fabricating a display device, which provides improved alignment between pixel electrodes and addressing lines, and reduces the number of photo processing steps needed to fabricate such a device.
A pixel cell is provided having a thin film transistor structure formed on a substrate and addressing lines (e.g., gate and data (signal) lines) patterned on the thin film transistor structure. A first patterned layer of a transparent conductive material covers the data (signal) line and is used to pattern the data metal and a doped silicon layer to form a channel region by performing a channel region etch of a back channel etch (BCE) type TFT. A dielectric layer or layers are formed over the pixel cell, and a via hole is patterned down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure. The self-alignment is preferably achieved by a back exposure of a negative tone photoresist.
In alternate embodiments, the first patterned layer of transparent conductor material may include a landing portion to provide a connection to the second layer of transparent conductor material through the via hole. The landing portion may be formed on a transparent material. The transparent material may include the substrate. The transistor structure may include a gate dielectric layer and the landing portion may be formed on the gate dielectric layer. The second layer of transparent conductive material may be patterned to form a pixel electrode of a liquid crystal display cell. The transistor structure may be opaque to provide the self-alignment of the second layer of transparent conductive material by a back-exposure operation. The transistor structure may include a back channel etch-type transistor.
A method for forming a pixel cell, includes the steps of forming a thin film transistor structure on a substrate, patterning a signal line which connects to the thin film transistor structure, patterning a first transparent conductor layer which connects to the signal line, depositing a dielectric layer over the pixel cell, forming a via hole in the dielectric layer which exposes a portion of the first transparent conductor layer, depositing a second transparent conductor layer on the dielectric layer and in the via hole to connect the second transparent conductor layer to the first transparent conductor layer, and patterning the second transparent conductor layer to form a pixel electrode.
In other methods, the step of patterning the second transparent conductor layer may include the steps of forming a resist on the second transparent conductor layer and back-exposing the resist by employing the transistor structure as a photo mask. The method may include the step of front exposing the resist layer to pattern other portions of the second transparent conductor layer. The step of patterning the second transparent conductor layer may include the steps of forming a resist on the second transparent conductor layer and front exposing the resist by employing a photo mask. The step of forming a thin film transistor structure on a substrate may include the steps of forming a gate metal on the substrate, forming a gate dielectric layer over the gate metal, and forming a semiconductor layer on the gate dielectric. The first conductive layer may include a landing portion formed on the gate dielectric layer and the step of depositing the second transparent conductor layer on the dielectric layer and in the via hole may include connecting the landing portion of the first conductor layer with the second conductor layer. The method may include the step of forming ohmic contacts in the semiconductor layer. The first conductive layer may include a landing portion formed on the substrate and the step of depositing the second transparent conductor layer on the dielectric layer and in the via hole may include connecting the landing portion of the first conductor layer with the second conductor layer. The step of patterning a first transparent conductor layer may include the steps of patterning a gap in the first transparent conductor layer over the signal line, and etching the signal line in the gap. The signal line may be formed on the thin film transistor structure and the thin film transistor structure may include a semiconductor layer and an ohmic contact layer formed on the semiconductor layer, and the step of etching the signal line in the gap may include the step of etching through the signal line, through the ohmic contact layer and into the semiconductor region to form a channel region of the thin film transistor structure.